Features SDS Sigma series

1 features

1.1 cpu
1.2 memory
1.3 peripherals

1.3.1 mass storage
1.3.2 communications
1.3.3 system control unit


1.4 carnegie mellon sigma 5

features
cpu

sigma systems provided range of performance, doubling sigma 5, slowest, sigma 9 model 3, fastest. example, 32-bit fixed point multiply times ranged 7.2 3.8 μs; 64-bit floating point divide ranged 30.5 17.4 μs.

most sigma systems included 2 or more blocks of 16 general-purpose registers. switching blocks accomplished single instruction (lpsd), providing fast context switching, since registers not have saved , restored.

memory

memory in sigma systems can addressed individual bytes, halfwords, words, or doublewords.

all 32-bit sigma systems except sigma 5 , sigma 8 used memory map implement virtual memory. following description applies sigma 9, other models have minor differences.

the effective virtual address of word 17 bits wide. virtual addresses 0 thru 15 reserved reference corresponding general purpose register, , not mapped. otherwise, in virtual memory mode high-order 8 bits of address, called virtual page number, used index array of 256 13-bit memory map registers. thirteen bits map register plus remaining 9 bits of virtual address form address used access real memory.

access protection implemented using separate array of 256 two-bit access control codes, 1 per virtual page (512 words), indicating combination of read/write/execute or no access page.

independently, array of 256 2-bit access control registers first 128k words of real memory function lock-and-key system in conjunction 2 bits in program status doubleword. system allows pages marked unlocked , or key master key . otherwise key in psd had match lock in access register in order reference memory page.

peripherals

input/output accomplished using control unit called iop (input-output processor). iop provides 8-bit data path , memory. systems support 8 iops, each of can attach 32 device controllers.

an iop can either selector i/o processor (siop) or multiplexer i/o processor (miop). siop provides data rate 1.5 megabytes per second (mbps), allows 1 device active @ time. miop, intended support slow speed peripherals allows 32 devices active @ time, provides .3 mbps aggregate data rate.

mass storage

rad cover open , disk pulled out maintenance

the primary mass storage device, known rad (random-access disk), contains 512 fixed heads , large (approx 600 mm/24 in diameter) vertically mounted disk spinning @ relatively low speeds. because of fixed head arrangement, access quite fast. capacities range 1.6 6.0 megabytes , used temporary storage. large-capacity multi-platter disks employed permanent storage.

communications

the sigma 7611 character oriented communications subsystem (coc) supports 1 7 line interface units (lius). each liu can have 1 8 line interfaces capable of operating in simplex, half-duplex, or full-duplex mode. coc intended low medium speed character oriented data transmissions.

system control unit

the system control unit (scu) microprogrammable data processor can interface sigma cpu, , peripheral , analog devices, , many kinds of line protocol. scu executes horizontal microinstructions 32-bit word length. cross-assembler running on sigma system can used create microprograms scu.

carnegie mellon sigma 5

the sigma 5 computer owned carnegie mellon university donated computer history museum in 2002. system consists of 5 full-size cabinets monitor, control panel , printer. possibly last surviving sigma 5 still operational.

the sigma 5 sold us$300,000 16 kilowords of random-access magnetic-core memory, optional memory upgrade 32 kw additional $50,000. hard disk drive had capacity of 3 megabytes.